Drop recipe creating method, database creating method and medium

ABSTRACT

According to one embodiment, a plurality of test drop recipes are first created based on design data on a semiconductor integrated circuit. Based on a defect inspection result of a pattern of a hardening resin material, which is formed by pressing a template on which patterns of the semiconductor integrated circuit are formed onto the hardening resin material applied to a substrate to be processed by use of the test drop recipes, a drop recipe with least defects is selected per press position on the substrate to be processed from the test drop recipes. The selected drop recipes for respective press positions are collected per functional circuit block configuring the semiconductor integrated circuit, thereby to generate a drop recipe creation assistant database.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a reissue of U.S. Pat. No. 8,560,977, issued on Oct.15, 2013, from U.S. patent application Ser. No. 13/238,615, which isbased upon and claims the benefit of priority from the prior JapanesePatent Application No. 2010-260293, filed on Nov. 22, 2010; the. Theentire contents of which the above-identified applications areincorporated herein by reference.

FIELD

Embodiments described herein relate generally to a drop recipe creatingmethod, a database creating method and a medium.

BACKGROUND

A nanoimprint lithography technique (which will be simply referred to asnanoimprinting below) is known as a semiconductor integrated circuitmanufacturing technique. The nanoimprinting is a technique for pressinga template on which a pattern of a semiconductor integrated circuit isformed onto a resist applied on a semiconductor wafer, and therebytransferring the pattern formed on the template onto the resist. Theapplication amount of a resist material is controlled based on a droprecipe defining an application amount distribution of the resistmaterial onto the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram for explaining a transferring step bynanoimprinting;

FIG. 1B is a diagram for explaining the transferring step by thenanoimprinting;

FIG. 1C is a diagram for explaining the transferring step by thenanoimprinting;

FIG. 2 is an overhead view of one wafer 100;

FIG. 3 is a diagram for explaining a pattern to be imprinted onto animprint position Z;

FIG. 4 is a diagram for explaining one exemplary data structure of GDSdata;

FIG. 5 is a diagram for explaining a structure of a database creatingapparatus;

FIG. 6 is a diagram for explaining one exemplary data structure of adrop recipe creation assistant database;

FIG. 7 is a diagram illustrating one exemplary correspondence between aline width and a discharge amount described in discharge amountcorrection data;

FIG. 8 is a flowchart for explaining a database creating method;

FIG. 9 is a diagram for explaining a structure of a drop recipe creatingapparatus;

FIG. 10 is a flowchart for explaining a drop recipe creating method;

FIG. 11 is a diagram illustrating one exemplary template pattern inwhich a resist material flows in a specific direction; and

FIG. 12 is a diagram for explaining exemplary drop recipes forrespective IPs configuring the drop recipe creation assistant database.

DETAILED DESCRIPTION

In general, according to one embodiment, a plurality of test droprecipes are first created based on design data on a semiconductorintegrated circuit. Based on a defect inspection result of a pattern ofa hardening resin material, which is formed by pressing a template onwhich patterns of the semiconductor integrated circuit are formed ontothe hardening resin material applied to a substrate to be processed byuse of the test drop recipes, a drop recipe with least defects isselected per press position on the substrate to be processed from thetest drop recipes. The selected drop recipes for respective presspositions are collected per functional circuit block configuring thesemiconductor integrated circuit, thereby to generate a drop recipecreation assistant database.

Exemplary embodiments of a drop recipe creating method, a databasecreating method and a medium will be explained below in detail withreference to the accompanying drawings. The present invention is notlimited to the following embodiments.

A drop recipe creating method, a database creating method and arecording medium according to the embodiments will be described below indetail with reference to the accompanying drawings. The presentinvention is not limited to the embodiments.

A typical transferring step by nanoimprinting will be first described.FIGS. 1A to 1C are diagrams for explaining the transferring step bynanoimprinting. Optical nanoimprinting for hardening a resist (opticalhardening resin material) by ultraviolet light irradiation will bedescribed herein by way of example, but the embodiments are applicableto thermal nanoimprinting for hardening a resist (thermal hardeningresin material) by heating.

In the transferring step, as illustrated in FIG. 1A, a resist material101 (exemplary hardening resin material) is first applied on a wafer 100to be processed (exemplary substrate to be processed). An imprintingapparatus has a nozzle which is two-dimensionally driven in parallel tothe wafer 100 and is directed for discharging the resist material 101,and can locally change the application amount of the resist material 101based on a drop recipe defining an application amount distribution ofthe resist material. The drop recipe is created based on design data ona design pattern (or resist pattern or template pattern may bepossible). The drop recipe is defined such that the application amountis large at a resist pattern with high density and the applicationamount is small at a resist pattern with low density. The applicationamount distribution in the drop recipe is defined by the amount of onedrop of resist material (the discharge amount) discharged from thenozzle and a discharge position per droplet, for example. In FIG. 1A,with the imprinting apparatus of this type, the droplets of the resistmaterial 101 drop on concave parts of a template 102.

Subsequently, the template 102 is pressed onto the wafer 100 on whichthe resist material 101 is applied. The resist material 101 enters theconcave parts of the template pattern formed on the template 102 due toa capillary action. After the resist material 101 fully enters thetemplate pattern, an ultraviolet light is irradiated from above thetemplate 102 as illustrated in FIG. 1B. The template 102 is made of amaterial such as quartz capable of transmitting an ultraviolet light (UVlight), and the UV light irradiated from above the template 102transmits the template 102 to be irradiated onto the resist material101. The resist material 101 is hardened by the UV light irradiation.

After the resist material 101 is hardened, the template 102 is separatedtherefrom and the resist pattern is formed by the hardened resistmaterial 101 on the wafer 100 as illustrated in FIG. 1C.

The resist material 101 formed on the wafer 100 is polished by chemicalmechanical polishing in a later step. In the chemical mechanicalpolishing, a different force is applied between the resist pattern atthe outermost of the wafer 100 and the resist pattern at the center ofthe wafer 100, and thus the resist pattern formed on the wafer 100cannot be planarized well. Thus, it is ideal that the entire wafer 100is covered with a uniform pattern.

FIG. 2 is an overhead view of one wafer 100. Each of the rectanglesillustrated in FIG. 2 is an area in which the resist pattern is formedby one imprinting (which will be referred to as one-shot area below). Asillustrated, the wafer 100 is imprinted at shifted imprint positionsmultiple times so that the resist pattern is formed on substantially theentire wafer 100. The imprint position Z is out of the periphery of thewafer 100, which is further outside the outermost one-shot area, andone-shot imprinting cannot be performed on the imprint position Z, butthe imprinting is performed thereon.

When the same drop recipe is used to perform imprinting on the outermostand the center of the wafer 100, the resist material spreads out of theouter periphery of the wafer 100 when the imprinting is performed on theoutermost of the wafer 100. The excess resist material leads to acontamination (particles) in a later step. Thus, when the imprinting isperformed on the imprint position at the outermost of the wafer 100, adifferent drop recipe from that for the center of the wafer 100 needs tobe used.

In the example of FIG. 2, although for the imprint position A, foursides of the one-shot area are adjacent to other one-shot areas, evenwhen the same drop recipe is used for a plurality of imprint positionsA, the resist material does not excessively spread. In other words, thesame resist recipe can be used for the imprint positions A thereby toperform imprinting. However, the same drop recipe as the drop recipeused for the imprint positions A cannot be used for the imprintpositions B, the imprint positions C and the imprint positions Z at theoutermost. Even at the outermost imprint positions, the same drop recipecannot be used for the imprint positions B whose one or two sides arenot adjacent to other one-shot areas, the imprint positions C whosethree sides are not adjacent to other one-shot areas and the imprintpositions Z for which a full resist pattern for one shot cannot beimprinted. Therefore, different drop recipes are prepared for theimprint positions A, B, C and Z, respectively.

FIG. 3 is a diagram for explaining a pattern to be imprinted on theimprint position Z. In recent years, there has been employed a designingmethod for creating design data of an entire semiconductor integratedcircuit at a higher speed by previously designing circuit blocks(functional circuit blocks) having a certain function and appropriatelycombining the design data on the circuit blocks. The previously-designedcircuit block is called semiconductor IP (which will be simply referredto as IP below) and is to be dealt with. A chip 103 formed with one-shotillustrated in FIG. 3 is configured in combination of IPs of cell a,test circuit a, test circuit b and peripheral circuits a to e. Theperipheral circuits a, d and e in the chip 103 are imprinted on theright imprint position Z out of the imprint positions Z illustrated inFIG. 3.

FIG. 4 is a diagram for explaining one exemplary data structure of GDSdata as one example of the design data. GDS data 41 has a plurality oflayers, and can hold the design data on different layers configuring asemiconductor integrated circuit such as an insulative oxide film layerand a metal layer in different layers. The GDS data comprises layers inwhich text is described, and a name, an arrangement position and anarrangement direction per IP are defined (the name, the arrangementposition and the arrangement direction are collectively referred to asattribute information below). In the example of FIG. 4, attributeinformation on two IPs including the circuit block 1 and the circuitblock 2 is defined in the layer 41-1.

When the IP is divided into smaller circuit blocks, attributeinformation on the smaller circuit blocks is further defined in thelayer in which the attribute information is defined. For example, when alarge circuit block comprises a plurality of identical circuit blockssmaller than the large circuit block, attribute information on thesmaller circuit blocks is defined. The items of attribute information onthe circuit blocks are associated with each other by way of a hierarchystructure. In the example of FIG. 4, in the layer 41-1, attributeinformation on the circuit blocks 11, 12 and 13 is defined at a lowertier than the attribute information on the circuit block 1, andattribute information on four circuit blocks 121 is defined at a lowertier than the attribute information on the circuit block 12.

Design data defining a pattern shape is defined for the smallest circuitblock. The design data is held in a different layer for the same GDSdata. In the example of FIG. 4, the three-layer design data on thecircuit blocks 121 is illustrated as held in the layers 41-2, the layer41-3 and the layer 41-4. Though not illustrated, the circuit block 11and the circuit block 13 also correspond to the smallest circuit blockand the design data on the blocks is held in the GDS data.

Since the GDS data is configured as described above, the total patternsfor one template are grasped by arranging all the items of design dataon the minimum components based on the attribute information defined inthe layer 41-1. In other words, since all the layers including thelayers describing therein the design data need to be read for creatingthe drop recipes, it takes much time to create one drop recipe. In orderto obtain an optimum drop recipe per imprint position for manufacturinga semiconductor integrated circuit, multiple test drop recipes need tobe created thereby to actually perform imprinting, and a best droprecipe needs to be selected per imprint position from the test droprecipes in terms of the number of defects, and thus there is a problemthat a time required to decide drop recipes to be used for actualmanufacture increases depending on the number of test drop recipes.

According to the embodiments of the present invention, in order tosimplify the work of creating the drip recipes, an optimum drop recipeper imprint position is obtained per IP and the obtained drop recipe ismade to a database. When a new semiconductor integrated circuit ismanufactured, a drop recipe is extracted from the created database perIP configuring the new semiconductor integrated circuit and is combinedbased on the attribute information defined in the layer 41-1 so that thedrop recipes for the respective imprint positions can be created for thenew semiconductor integrated circuit.

FIG. 5 is a diagram for explaining a structure of a database creatingapparatus for creating such a database (drop recipe creation assistantdatabase). As illustrated, a database creating apparatus 200 comprises aCPU 1, RAM (Random Access Memory) 2, ROM (Read Only Memory) 3, anexternal storing device 4, an input unit 5 and an output unit 6. The CPU1, the RAM 2, the ROM 3, the external storing device 4, the input unit 5and the output unit 6 are interconnected via a bus line.

The CPU 1 executes a database creating program 21 as computer programfor creating a drop recipe creation assistant database 45. The inputunit 5 comprises a mouse and a keyboard, and is input the operations ofthe database creating apparatus 200 by a user. The operation informationinput into the input unit 5 is sent to the CPU 1.

The external storing device 4 is configured of a hard disk drive or thelike, and is used as a data input/output device of the CPU 1.Specifically, the external storing device 4 previously stores thereinthe GDS data 41 on a semiconductor integrated circuit to bemanufactured. The external storing device 4 stores therein the test droprecipes (test drop recipe group 42) which are created by the CPU 1changing the discharge amount and the discharge position, respectively.

The test drop recipe group 42 is used by the user for experimentallyproducing the resist patterns. After the experimental producing, theuser inputs defect inspection results (defect inspection result group43) and CD (Critical Dimension) measurement values (CD measurement valuegroup 44) for the experimentally-produced resist patterns into theexternal storing device 4. The defect inspection result and the CDmeasurement value per test drop recipe are input per imprint position.

The CPU 1 refers to the defect inspection result group 43 and the CDmeasurement value group 44 to select a best drop recipe per imprintposition from the test drop recipe group 42 one by one, therebygenerating the drop recipe creation assistant database 45 in theexternal storing device 4.

FIG. 6 is a diagram for explaining one exemplary data structure of thedrop recipe creation assistant database 45. As illustrated, the droprecipe creation assistant database 45 holds a drop recipe per IP (IPa,IPb, IPc and the like) at each imprint position. Since a unique name perIP and a unique name per imprint position are incorporated in the dataor a file name, each drop recipe is associated with the IP and theimprint position so that the IP name and the imprint position can beidentified.

A variation in line width occurs in individual templates to be delivereddue to a variation in process during template manufacture. In a firstembodiment, a representative line width of the used template isassociated with the drop recipe per IP. A template manufacturertypically inspects the manufactured templates and delivers them with theinspection result as performance report. The representative line widthof the template can be obtained from the attached performance reportduring the delivery of the templates.

The CPU 1 finds a correspondence between a line width of the templatepattern and a discharge amount by which a resist pattern with a desiredline width can be obtained from the line width from the test drop recipegroup 42, the defect inspection result group 43 and the CD measurementvalue group 44, and outputs the found correspondence as discharge amountcorrection data 46 to the external storing device 4. FIG. 7 is a diagramillustrating one exemplary correspondence between the line width and thedischarge amount described in the discharge amount correction data 46.As illustrated, the correspondence indicates that as the line width islarger, the discharge amount is smaller.

The user creates drop recipes for one template and adjusts (corrects)the discharge amounts of the created drop recipes based on the dischargeamount correction data 46, thereby restricting a variation in a finishedshape due to the variation in line width of individual templates for thesame design data.

The output unit 6 is a display device such as liquid crystal monitor,and displays output information such as operation screen for an operatorbased on the instructions from the CPU 1.

The database creating program 21 executed by the database creatingapparatus 200 may be stored on a computer connected to a network such asthe Internet and may be downloaded via the network to be provided ordistributed. The database creating program 21 may be provided ordistributed via the network such as the Internet. The database creatingprogram 21 may be previously incorporated in the ROM 3 or the externalstoring device 4 to be provided to the database creating apparatus 200.The database creating program 21 may be recorded in a recording mediumsuch as a CD-ROM to be provided or distributed.

A database creating method for creating the drop recipe creationassistant database 45 by use of the database creating apparatus 200 willbe described below.

FIG. 8 is a flowchart for explaining the database creating method. Asillustrated, the CPU 1 first acquires the GDS data 41 from the externalstoring device 4 (step S1). The CPU 1 interprets all the layers of theobtained GDS data 41 to generate the test drop recipe group 42 (stepS2).

The user uses all the test drop recipes in the test drop recipe group 42for all the imprint positions in the test drop recipe group 42 perimprint position to experimentally produce the resist patterns (stepS3), and makes a CD measurement and a defect inspection on theexperimentally-produced resist patterns (step S4). The user stores theobtained defect inspection result group 43 and CD measurement valuegroup 44 in the external storing device 4.

The CPU 1 acquires the defect inspection result group 43 and the CDmeasurement value group 44 stored in the external storing device 4 (stepS5), and selects a best drop recipe per imprint position from among thetest drop recipe group based on the acquired defect inspection resultgroup 43 and CD measurement value group 44 (step S6). The CPU 1decomposes the selected drop recipe per IP (step S7). The CPU 1 eitherof or both inverts and rotates the drop recipe decomposed and acquiredper IP in a predetermined reference direction (step S8). Thus, for therotation, the drop recipes for the same IPs and mirror-symmetrical IPscan be managed as the drop recipe for one IP, causing the data size tobe reduced.

The CPU 1 generates the drop recipe creation assistant database 45 withthe IP name of the drop recipe per IP, the name of the imprint positionand the representative line width of the template used for theexperimental producing (step S9). The CPU 1 generates the dischargeamount correction data 46 (step S10). Then, the database creating methodends.

In this way, according to the first embodiment of the present invention,since there is configured such that the test drop recipes (test droprecipe group 42) are created based on the design data (GDS data 41), adrop recipe with least defects is selected per imprint position from thetest drop recipes based on the defect inspection results (defectinspection result group 43) of the resist patterns experimentallyproduced by use of the created test drop recipes, and the selected droprecipe is made to a database per IP to generate the drop recipe creationassistant database 45, when drop recipes for a new semiconductorintegrated circuit are created, the resist recipe can be created bycombining the drop recipes for the respective IPs configuring the newsemiconductor integrated circuit based on the attribute information ofthe GDS data 41 on the new semiconductor integrated circuit so that theGDS data 41 for all the layers does not need to be read, therebycreating the drop recipes for the new semiconductor integrated circuitwith ease and at a high speed. Since the drop recipe creation assistantdatabase 45 holds the drop recipe per IP at each imprint position, thedrop recipes for the new semiconductor integrated circuit can be createdat the respective imprint positions. Since the drop recipe creationassistant database 45 holds the drop recipe per IP, although theone-shot imprinting is not possible at the imprint position Z, only theattribute information on the imprint-possible parts may be used toarrange the drop recipe per IP, thereby creating the drop recipe usedfor the imprint position Z with ease and at a high speed.

FIG. 9 is a diagram for explaining a structure of a drop recipe creatingapparatus for creating drop recipes for a template of a newsemiconductor integrated circuit by use of the drop recipe creationassistant database 45. As illustrated, a drop recipe creating apparatus300 comprises a similar computer structure to the database creatingapparatus 200, and is different therefrom in the contents stored in theexternal storing device 4 and the programs to be executed by the CPU 1.

The CPU 1 uses the drop recipe creation assistant database 45 to executea drop recipe creating program 22 as computer program for creating adrop recipe (drop recipe group 47) per imprint position. The input unit5 comprises a mouse and a keyboard, and is input the operations of thedrop recipe creating apparatus 300 by the user. The operationinformation input into the input unit 5 is sent to the CPU 1.

The external storing device 4 is configured of a hard disk drive or thelike, and is used as a data input/output device of the CPU 1.Specifically, the external storing device 4 previously stores thereinthe GDS data 41 on a semiconductor integrated circuit to be newlymanufactured, the drop recipe creation assistant database 45 and thedischarge amount correction data 46. The external storing device 4stores therein the drop recipe group 47 created by the CPU 1.

The output unit 6 is a display device such as a liquid crystal monitor,and displays output information such as an operation screen for theoperator based on the instructions from the CPU 1.

The drop recipe creating program 22 executed by the drop recipe creatingapparatus 300 may be stored on a computer connected to the network suchas the Internet and may be downloaded via the network to be provided ordistributed. The drop recipe creating program 22 may be provided ordistributed via the network such as the Internet. The drop recipecreating program 22 may be previously incorporated in the ROM 3 or theexternal storing device 4 to be provided to the drop recipe creatingapparatus 300. The drop recipe creating program 22 may be recorded in arecording medium such as a CD-ROM to be provided or distributed.

FIG. 10 is a flowchart for explaining a drop recipe creating methodimplemented by use of the drop recipe creating apparatus 300. Asillustrated, the CPU 1 first acquires the GDS data 41 from the externalstoring device 4 (step S21). Then, the CPU 1 extracts the attributeinformation on IPs configuring a semiconductor integrated circuit to bemanufactured from the layer 41-1 defining therein the attributeinformation contained in the GDS data 41 (step S22).

The CPU 1 designates one imprint position on the wafer 100 (step S23).The CPU 1 extracts a drop recipe for an IP configuring the semiconductorintegrated circuit to be manufactured at the designated position fromamong the drop recipe creation assistant database 45 (step S24).Specifically, the CPU 1 searches for the drop recipe creation assistantdatabase 45 with the IP name contained in the extracted attributeinformation and the designated imprint position as search keys, and thenextracts a drop recipe.

The CPU 1 arranges the extracted drop recipe according to thearrangement position and the arrangement direction described in theattribute information, and completes the drop recipe for the one-shot atthe designated imprint position (step S25).

The CPU 1 decides whether all the imprint positions have been designated(step S26). When undesignated imprint positions remain (in step S26,No), the CPU 1 proceeds to step S23 to designate one of the undesignatedimprint positions. When all the imprint positions have been designated(in step S26, Yes), the CPU 1 is input the representative line width ofthe template used for manufacture (step S27). The representative linewidth is input from the input unit 5 by the user, for example. The CPU 1uses the input representative line width to search for the dischargeamount correction data 46, and calculates the discharge amountcorresponding to the representative line width (step S28). The CPU 1corrects the discharge amount of the drop recipe per imprint position bythe calculated discharge amount (step S29) so that the drop recipe perimprint position (drop recipe group 47) is completed.

In this way, according to the second embodiment of the presentinvention, since there is configured such that the arrangement positionsof the IPs configuring the semiconductor integrated circuit areextracted from the GDS data 41, the drop recipes of the IPs configuringthe semiconductor integrated circuit at desired imprint positions areextracted from the drop recipe creation assistant database 45, and theextracted drop recipes are arranged based on the extracted correspondingarrangement position to generate the drop recipes for the template ofthe semiconductor integrated circuit, all the layers configuring the GDSdata 41 do not need to be read each time the drop recipe is created,thereby creating the drop recipes with ease and at a high speed.

Since the discharge amount of the hardening resin material is correctedin the drop recipes for the template based on the representative linewidth of the template of the semiconductor integrated circuit, theimprinting can be performed without creating the drop recipe perindividual template.

The features of the resist material, which influence the number ofdefects, include contraction rate, elastic force, base material adhesionforce, charging property, solvent resistance, fluorine content rate, andthe like. The features have a relationship in which one feature isenhanced while other feature deteriorates, and thus a most desirablecomposition is not possible for all the features. Thus, the imprintingis typically performed by use of one kind of resist material whosecomposition is adjusted such that the number of defects in an one-shotis as small as possible.

In recent years, there has been developed an applying apparatus fordropping multiple kinds of resist materials in one template. When theapplying apparatus is used, an optimum resist material can be selectedand locally applied. When the test drop recipe group 42 is created inthe first embodiment (step S2), the resist patterns for which differentresist materials are designated, respectively, may be created.

In this way, the drop recipe creation assistant database 45 isconfigured by the drop recipes optimized by the resist materials so thatthe drop recipes by which the resist material is locally changed can becreated with ease and at a high speed.

For example, it is highly likely that the IPs such as memory cellscontaining many lines and spaces are charged due to friction duringseparation and the lines fall down due to the charges, causing defects.The resist material whose composition is not easily charged can be usedfor the IPs in contrast to other IPs.

As described above, according to the third embodiment of the presentinvention, when the drop recipe is defined based on the GDS data whilemultiple anisotropic patterns are remarkably deflected and arranged likethe lines and patterns, the resist material flows out in a specificdirection when the template is pressed, and thus the resist materialdoes not spread over the entire template as intended, which mayconsequently cause an increase in defects.

For example, the template pattern illustrated in FIG. 11 is an exemplarytemplate pattern in which the resist material flows out in a specificdirection. The black rectangles indicate the formed resist patterns. Thetemplate pattern includes four IPs including IPa, IPb, IPc and IPd eachcomprising the lines and patterns. When the lines and patterns arepressed, the resist material easily flows along the lines. Thus, theresist material tends to flow into the hatched areas in FIG. 11.

In order to prevent the resist material from flowing in the specificdirection, the drop recipe per IP configuring the drop recipe creationassistant database may be created such that the highly-viscous resistmaterial is arranged in the direction in which the resist materialeasily flows.

FIG. 12 is a diagram for explaining exemplary drop recipes for IPsconfiguring the drop recipe creation assistant database. As illustrated,in the drop recipe per IP (IPa to IPd), a resist material 101-1, whichis selected for reducing the number of defects, is applied to the lines.A resist materials 101-2 with a higher viscosity than the resistmaterial 101-1 is applied at the ends of the lines in line. Thus, evenwhen the resist material 101-1 flows out in the line direction, the flowis blocked by the barriers formed by the resist material 101-2, therebypreventing the resist material 101-1 from flowing out in the specificdirection. There is described in the figure that the resist material101-2 is applied at the ends of the lines in line, but the drop recipemay be created such that the resist material 101-2 is applied along allthe sides to surround the pattern per IP.

In this way, according to the fourth embodiment of the presentinvention, the test drop recipe is such that a resist material with ahigher viscosity than the resist material is arranged at the positionswhere the resist material is prevented from flowing during theimprinting per IP configuring a semiconductor integrated circuit,thereby preventing the resist material from flowing in the specificdirection per IP.

There has been described in the first to fourth embodiments that thedrop recipe creation assistant database 45 is configured by the droprecipes for the respective IPs, but any circuit block in any tier whoseattribute information is defined in the GDS data 41 may be used as unitof the drop recipe held by the drop recipe creation assistant database45.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A drop recipe creating method comprising: storing, by a memory, a database holding first drop recipes for respective functional circuit blocks at respective imprint positions; extracting, by a processor, arrangement positions of a plurality of functional circuit blocks configuring a semiconductor integrated circuit on the semiconductor integrated circuit from design data of the semiconductor integrated circuit stored in the memory; extracting, by the processor, the first drop recipes for each of the functional circuit blocks configuring the semiconductor integrated circuit at designated imprint positions from the database; creating, by the processor, a second drop recipe of the semiconductor integrated circuit by arranging the extracted first drop recipes based on the extracted corresponding arrangement positions and combining the arranged first drop recipes; and outputting, by the processor, the second drop recipe to the memory.
 2. The drop recipe creating method according to claim 1, comprising: extracting, by the processor, arrangement directions of the functional circuit blocks configuring the semiconductor integrated circuit from the design data; and when creating the second drop recipe, arranging, by the processor, the extracted first drop recipes of the functional circuit blocks based on the extracted arrangement positions and arrangement directions.
 3. The drop recipe creating method according to claim 1, further comprising correcting, by the processor, the discharge amount of a hardening resin material in the second drop recipe based on a representative line width of the semiconductor integrated circuit.
 4. A drop recipe creating method used in transferring a pattern to a semiconductor wafer, wherein a drop recipe defines one or more application amount distributions of one or more resist materials on a semiconductor wafer, the method comprising: storing, in a memory, a database of first drop recipes, wherein the first drop recipes are each associated with one or more first patterns and with one or more imprint positions; extracting, by a processor, arrangement positions on the semiconductor wafer of second patterns, the second patterns configuring patterns to be formed on the semiconductor wafer; extracting from the database, by the processor, at least two of the first drop recipes for at least two of the second patterns at designated imprint positions on the semiconductor wafer; arranging, by the processor, the extracted first drop recipes on the semiconductor wafer based on the extracted arrangement positions; creating, by the processor, a second drop recipe based on the arranged first drop recipes; and outputting, by the processor, the second drop recipe to the memory.
 5. The drop recipe creating method according to claim 4, further comprising: extracting, by the processor, arrangement directions of the second patterns based on the design data; wherein the extracted first drop recipes are also arranged based on the extracted arrangement directions.
 6. The drop recipe creating method according to claim 4, further comprising: determining, by the processor, one or more discharge amounts of the one or more resist materials based on a representative pattern width of the patterns to be formed on the semiconductor wafer.
 7. The drop recipe creating method according to claim 4, wherein the one or more application distribution amounts defined by the first drop recipes are related to at least one of a defect inspection result and a critical dimension measurement result of resist patterns created using a set of drop recipes including the first drop recipes.
 8. The drop recipe creating method according to claim 4, wherein the one or more application distribution amounts defined by at least one of the first drop recipes are related to one or more features of the resist materials.
 9. The drop recipe creating method according to claim 8, wherein the one or more features include at least one of contraction rate, elastic force, base material adhesion force, charging property, solvent resistance, and fluorine content rate.
 10. The drop recipe creating method according to claim 4, wherein the one or more application distribution amounts defined by at least one of the first drop recipes are related to a flowing direction of at least one of the resist materials in the associated first patterns.
 11. The drop recipe creating method according to claim 4, wherein at least some of the first patterns are associated with one or more circuit blocks.
 12. The drop recipe creating method according to claim 11, wherein the one or more circuit blocks include at least one functional circuit block.
 13. The drop recipe creating method according to claim 11, wherein the one or more circuit blocks include at least one test circuit block.
 14. The drop recipe creating method according to claim 11, wherein the one or more circuit blocks include at least one peripheral circuit block.
 15. The drop recipe creation method according to claim 4, wherein at least one of the first patterns includes one or more cell patterns.
 16. The drop recipe creation method according to claim 4, wherein at least one of the first patterns includes one or more lines.
 17. The drop recipe creation method according to claim 4, wherein one of the first recipes is associated with one of the first patterns to be formed on a first shot area of the semiconductor wafer and one of the first recipes is associated with one of the first patterns to be formed on a second shot area of the semiconductor wafer, wherein the first shot area of the semiconductor wafer does not include a periphery of the semiconductor wafer and the second shot area of the semiconductor wafer includes the periphery of the semiconductor wafer.
 18. The drop recipe creation method according to claim 17, wherein both of the first patterns to be formed on the first and the second shot areas of the semiconductor wafer include cell patterns.
 19. The drop recipe creation method according to claim 4, wherein the extracted first drop recipes are respectively associated with the first patterns in the database corresponding to the second patterns of which arrangement positions are extracted.
 20. A non-transitory computer readable medium comprising instructions that, when executed by a computer, cause the computer to perform a method of creating a drop recipe that defines one or more application distribution amounts of one or more resist materials on a semiconductor wafer, the method being used in transferring a pattern to a semiconductor wafer and comprising: storing, in a memory, a database including first drop recipes, wherein the first drop recipes are associated with one or more first patterns and with one or more imprint positions; extracting arrangement positions on the semiconductor wafer of second patterns, the second patterns configuring patterns to be formed on the semiconductor wafer; extracting from the database at least two of the first drop recipes for at least two of the second patterns at designated imprint positions; arranging the extracted first drop recipes based on the extracted arrangement positions; creating a second drop recipe based on the arranged first drop recipes; and outputting the second drop recipe to the memory.
 21. The medium according to claim 20, wherein the method further comprises: extracting arrangement directions of the second patterns based on the design data; wherein the extracted first drop recipes are also arranged based on the extracted arrangement directions.
 22. The medium according to claim 20, wherein the method further comprises: determining one or more discharge amounts of the resist materials based on a representative pattern width of the patterns to be formed on the semiconductor wafer.
 23. The medium according to claim 20, wherein the one or more application amount distributions defined by the first drop recipes are related to at least one of a defect inspection result and a critical dimension measurement result of resist patterns created using a set of drop recipes including the first drop recipes.
 24. The medium according to claim 20, wherein the one or more application amount distributions defined by at least one of the first drop recipes are related to one or more features of the resist materials.
 25. The medium according to claim 24, wherein the one or more features include at least one of contraction rate, elastic force, base material adhesion force, charging property, solvent resistance, and fluorine content rate.
 26. The medium according to claim 20, wherein the one or more application amount distributions defined by at least one of the first drop recipes are related to a flowing direction of at least one of the resist materials in the associated first patterns.
 27. The medium according to claim 20, wherein at least some of the first patterns are associated with one or more circuit blocks.
 28. The medium according to claim 27, wherein the one or more circuit blocks include at least one functional circuit block.
 29. The medium according to claim 27, wherein the one or more circuit blocks include at least one test circuit block.
 30. The medium according to claim 27, wherein the one or more circuit blocks include at least one peripheral circuit block.
 31. The medium according to claim 20, wherein at least one of the first patterns includes one or more cell patterns.
 32. The medium according to claim 20, wherein at least one of the first patterns includes one or more lines.
 33. The medium according to claim 20, wherein one of the first recipes is associated with one of the first patterns to be formed on a first shot area of the semiconductor wafer and one of the first recipes is associated with one of the first patterns to be formed on a second shot area of the semiconductor wafer, wherein the first shot area of the semiconductor wafer does not include a periphery of the semiconductor wafer and the second shot area of the semiconductor wafer includes the periphery of the semiconductor wafer.
 34. The medium according to claim 33, wherein both of the first patterns to be formed on the first and the second shot areas of the semiconductor wafer include cell patterns.
 35. The medium according to claim 20, wherein the extracted first drop recipes are respectively associated with the first patterns in the database corresponding to the second patterns of which arrangement positions are extracted. 